Thin film transistor and method for manufacturing a thin film transistor

ABSTRACT

The present disclosure relates to a thin film transistor and a manufacturing method thereof. The thin film transistor includes a substrate, a first semiconductor layer, a gate dielectric layer, and a gate electrode sequentially stacked on the substrate, the first semiconductor layer has a first portion located in a channel region of the thin film transistor and a second portion in source/drain regions of the thin film transistor and located on both sides of the first portion, the second portion and first sub-portions of the first portion adjacent to the second portion include an amorphous semiconductor material, a second sub-portion of the first portion between the first sub-portions includes a polycrystalline semiconductor material, and a second semiconductor layer located in the source/drain regions and in contact with the second portion, wherein a conductivity of the second semiconductor layer is higher than a conductivity of the amorphous semiconductor material.

CROSS REFERENCE TO RELATED APPLICATIONS

This patent application is a National Stage Entry of PCT/CN2019/076870filed on Mar. 4, 2019, the disclosure of which is incorporated byreference herein in its entirety as part of the present application.

BACKGROUND

The present disclosure relates to the field of display technology.Specifically, it relates to a thin film transistor and a method formanufacturing a thin film transistor.

Thin film transistors are widely used in the field of displaytechnology. A thin film transistor can drive a pixel of a displaydevice. A display device provided with a thin film transistor may haveadvantages such as high speed, high brightness, and high contrast.

BRIEF DESCRIPTION

Embodiments of the present disclosure provide a thin film transistor.The thin film transistor includes a substrate, a first semiconductorlayer, a gate dielectric layer, and a gate electrode sequentiallystacked on the substrate, wherein the first semiconductor layer has afirst portion located in a channel region of the thin film transistorand a second portion in source/drain regions of the thin film transistorand located on both sides of the first portion, and wherein the secondportion and first sub-portions, adjacent to the second portion, of thefirst portion include an amorphous semiconductor material, a secondsub-portion, between the first sub-portions, of the first portionincludes a polycrystalline semiconductor material, and a secondsemiconductor layer located in the source/drain regions and in contactwith the second portion, wherein a conductivity of the secondsemiconductor layer is higher than a conductivity of the amorphoussemiconductor material.

In some embodiments, the second semiconductor layer is in contact with asurface of the second portion facing the substrate.

In some embodiments, the second semiconductor layer is in contact with asurface of the second portion away from the substrate.

In some embodiments, a doping type of the first semiconductor layer anda doping type of the second semiconductor layer are an N-type, and anN-type carrier concentration of the second semiconductor layer isgreater than an N-type carrier concentration of the first semiconductorlayer.

In some embodiments, a doping type of the first semiconductor layer anda doping type of the second semiconductor layer are a P-type, and aP-type carrier concentration of the second semiconductor layer isgreater than a P-type carrier concentration of the first semiconductorlayer.

In some embodiments, a doping concentration of the first semiconductorlayer is between 10¹⁷ ions/cm³ and 10¹⁹ ions/cm³, and a dopingconcentration of the second semiconductor layer is between 10¹⁹ ions/cm³and 10²¹ ions/cm³.

In some embodiments, the polycrystalline semiconductor material includespolysilicon, and the amorphous semiconductor material includes amorphoussilicon.

In some embodiments, the thin film transistor further includes asource/drain electrode on a side of the second semiconductor layerfacing away from the second portion.

Some embodiments of the present disclosure also provide a method formanufacturing a thin film transistor. The method for manufacturing thethin film transistor includes forming a first semiconductor layer, agate dielectric layer, and a gate electrode sequentially on a substrate,wherein the first semiconductor layer has a first portion located in achannel region of the thin film transistor and a second portion locatedin source/drain regions of the thin film transistor and on both sides ofthe first portion, and wherein the second portion and a firstsub-portion of the first portion adjacent to the second portion includean amorphous semiconductor material, and a second sub-portion of thefirst portion between the first sub-portions includes a polycrystallinesemiconductor material, and forming a second semiconductor layer in thesource/drain regions and in contact with the second portion, wherein aconductivity of the second semiconductor layer is higher than aconductivity of the amorphous semiconductor material.

In some embodiments, forming the first semiconductor layer includesforming a first semiconductor material layer including the amorphoussemiconductor material, the first semiconductor material layer includinga middle portion as the first portion and edge portions as the secondportion, the edge portions being on both sides of the middle portion,and converting a portion, corresponding to the first sub-portion, of themiddle portion of the first semiconductor material layer into thepolycrystalline semiconductor material.

In some embodiments, the converting includes laser annealing theamorphous semiconductor material.

In some embodiments, the laser annealing includes using a micro lensarray mask.

In some embodiments, the method for manufacturing the thin filmtransistor further includes forming a source/drain electrode on a sideof the second semiconductor layer facing away from the second portions.

In some embodiments, forming the first semiconductor layer, the secondsemiconductor layer, and the source/drain electrode includes forming asource/drain electrode on the substrate, forming the secondsemiconductor layer on the source/drain electrode, and forming the firstsemiconductor layer on the second semiconductor layer.

In some embodiments, forming the first semiconductor layer, the secondsemiconductor layer, and the source/drain electrode includes forming thefirst semiconductor layer on the substrate, forming the secondsemiconductor layer on the first semiconductor layer, and forming thesource/drain electrode on the second semiconductor layer.

In some embodiments, forming the first semiconductor layer and thesecond semiconductor layer includes using CVD.

In some embodiments, the polycrystalline semiconductor material includespolysilicon, and the amorphous semiconductor material includes amorphoussilicon.

BRIEF DESCRIPTION OF THE DRAWINGS

To describe the technical solutions in the embodiments of the presentdisclosure more clearly, the accompanying drawings of the embodimentsare briefly described below. It should be understood that the drawingsdescribed below refer only to some embodiments of the presentdisclosure, and not to restrict the present disclosure, wherein:

FIG. 1 is a schematic view of a thin film transistor according to anembodiment of the present disclosure;

FIG. 2 is a schematic view of a thin film transistor according to anembodiment of the present disclosure;

FIGS. 3A-3B are schematic views of a method for forming a firstsemiconductor layer according to an embodiment of the presentdisclosure;

FIGS. 4A-4C are schematic views of a method for forming a firstsemiconductor layer, a second semiconductor layer, and source/drainelectrode according to an embodiment of the present disclosure; and

FIGS. 5A-5C are schematic views of a method for forming a firstsemiconductor layer, a second semiconductor layer, and source/drainelectrode according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make the technical solutions and advantages of theembodiments of the present disclosure more comprehensible, the technicalsolutions of the embodiments of the present disclosure are clearly andcompletely described below with reference to the accompanying drawings.Obviously, the described embodiments are only a part but not all of theembodiments of the present disclosure. Based on the describedembodiments of the present disclosure, all other embodiments obtained bythose skilled in the art without creative efforts shall also fall withinthe protection scope of the present disclosure.

As used herein and in the appended claims, the singular form of a wordincludes the plural, and vice versa, unless the context clearly dictatesotherwise. Thus, the references “a”, “an”, and “the” are generallyinclusive of the plurals of the respective terms. Similarly, the words“comprise”, “comprises”, and “comprising” are to be interpretedinclusively rather than exclusively.

For purposes of the description, hereinafter, the terms “upper”,“lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the disclosure, as it is oriented inthe drawing figures. The terms “overlying”, “atop”, “positioned on” or“positioned atop” means that a first element, such as a first structure,is present on a second element, such as a second structure, whereinintervening elements, such as an interface structure, e.g. interfacelayer, may be present between the first element and the second element.The term “contact” means that a first element, such as a firststructure, and a second element, such as a second structure, areconnected with or without any intermediary elements at the interface ofthe two elements.

FIG. 1 is a schematic view of a thin film transistor according to anembodiment of the present disclosure. As shown in FIG. 1, a thin filmtransistor according to an embodiment of the present disclosure includesa substrate 10, a first semiconductor layer 11, a gate dielectric layer12, and a gate electrode 13 which are sequentially stacked on thesubstrate 10. The first semiconductor layer 11 has a first portion P1located in a channel region R1 of the thin film transistor and a secondportion P2 located in source/drain regions R2 of the thin filmtransistor and located on both sides of the first portion P1. The secondportion P2 and a first sub-portion P11 of the first portion P1 adjacentto the second portion P2 include an amorphous semiconductor material. Asecond sub-portion P12 of the first portion P1 between the firstsub-portions P11 includes a polycrystalline semiconductor material. Thethin film transistor further includes a second semiconductor layer 14located in the source/drain regions R2 and in contact with the secondportion P2. The conductivity of the second semiconductor layer 14 ishigher than a conductivity of the amorphous semiconductor material. Forexample, according to some embodiments of the present disclosure, thefirst semiconductor layer may be unintentionally doped, and the secondsemiconductor layer may be N-type or P-type doped. According to anotherembodiment of the present disclosure, the first semiconductor layer mayhave the same doping type as the second semiconductor layer but have alower doping concentration.

For the thin film transistor according to an embodiment of the presentdisclosure, the second semiconductor layer 14 is not in direct contactwith the first portion P1 of the first semiconductor layer 11, which canreduce the hot carrier effect and reduce the leakage current of thetransistor.

As shown in FIG. 1, in an embodiment of the present disclosure, thesecond semiconductor layer 14 may be in contact with a surface 51 of thesecond portion P2 of the first semiconductor layer 11 remote from thesubstrate.

FIG. 2 is a schematic view of a thin film transistor according to anembodiment of the present disclosure. As shown in FIG. 2, in anembodiment of the present disclosure, the second semiconductor layer 14may be in contact with a surface S2, facing the substrate, of the secondportion P2 of the first semiconductor layer 11.

The thin film transistor may further include a source/drain electrode 15on a side, facing away from the second portion P2 of the firstsemiconductor layer 11, of the second semiconductor layer 14.

The doping type of the first semiconductor layer 11 and the secondsemiconductor layer 14 may be an N-type, and an N-type carrierconcentration of the second semiconductor layer 14 is greater than theN-type carrier concentration of the first semiconductor layer 11. Forexample, the doping concentration of the first semiconductor layer 11 isbetween 10¹⁷ ions/cm³ and 10¹⁹ ions/cm³. For example, the dopingconcentration of the second semiconductor layer may be between 10¹⁹ions/cm³ and 10²¹ ions/cm³. For example, when the material of the firstand second semiconductor layers is a tetravalent element semiconductormaterial such as silicon, the N-type dopant may be a pentavalentimpurity element such as phosphorus.

The doping type of the first semiconductor layer 11 and the secondsemiconductor layer 14 is a P-type, and a P-type carrier concentrationof the second semiconductor layer 14 is greater than a P-type carrierconcentration of the first semiconductor layer 11. For example, thedoping concentration of the first semiconductor layer 11 may be between10¹⁷ ions/cm³ and 10¹⁹ ions/cm³. For example, the doping concentrationof the second semiconductor layer may be between 10¹⁹ ions/cm³ and 10²¹ions/cm³. For example, when the material of the first and secondsemiconductor layers is a tetravalent element semiconductor material,such as silicon, the P-type dopant may be a trivalent impurity element,such as boron.

According to an embodiment of the present disclosure, thepolycrystalline semiconductor material may include polysilicon, and theamorphous semiconductor material may include amorphous silicon.

Embodiments of the present disclosure also provide a method formanufacturing a thin film transistor. A method for manufacturing a thinfilm transistor according to an embodiment of the present disclosureincludes forming a first semiconductor layer 11, a gate dielectric layer12, and a gate electrode 13 sequentially on a substrate 10, wherein thefirst semiconductor layer 11 has a first portion P1 located in a channelregion R1 of the thin film transistor and a second portion P2 located insource/drain regions R2 of the thin film transistor and on both sides ofthe first portion, and forming a second semiconductor layer 14 in thesource/drain regions R2 and in contact with the second portions P2. Thesecond portion P2 and first sub-portions P11 of the first portion P1adjacent to the second portion P2 include an amorphous semiconductormaterial, and a second sub-portion P12 of the first portion P2 betweenthe first sub-portions P2 includes a polycrystalline semiconductormaterial. A conductivity of the second semiconductor layer 14 is higherthan a conductivity of the amorphous semiconductor material.

For the method for manufacturing a thin film transistor according tosome embodiments of the present disclosure, the second semiconductorlayer 14 is not in direct contact with the first portion P1 of the firstsemiconductor layer 11, which can reduce the hot carrier effect andreduce the leakage current of the transistor. FIGS. 3A-3B are schematicviews of a method for forming a first semiconductor layer according toan embodiment of the present disclosure. As shown in FIGS. 3A-3B,forming the first semiconductor layer may include:

S31. As shown in FIG. 3A, forming a first semiconductor material layer11′ including the amorphous semiconductor material. The firstsemiconductor material layer 11′ includes a middle portion P1′ as thefirst portion P1 and edge portions P2′, as the second portion P2, onboth sides of the middle portion P1′.

S33. As shown in FIG. 3B, converting a portion P11′, corresponding tothe first sub-portion P11, of the middle portion P1′ of the firstsemiconductor material layer 11′ into a polycrystalline semiconductormaterial.

According to an embodiment of the present disclosure, laser annealingmay be used to convert an amorphous semiconductor material into apolycrystalline semiconductor material (i.e., perform apolycrystallization process). For example, a Micro Lens Array (MLA) maskcan be used for laser annealing.

The method for manufacturing a thin film transistor according to anembodiment of the present disclosure further includes forming asource/drain electrode 15 on a side of the second semiconductor layer 14facing away from the second portions P2. FIGS. 4A-4C are schematic viewsof a method for forming a first semiconductor layer, a secondsemiconductor layer, and a source/drain electrode according to anembodiment of the present disclosure. In the embodiment shown in FIGS.4A-4C, forming the first semiconductor layer, the second semiconductorlayer, and the source/drain electrode includes:

S41. As shown in FIG. 4A, forming source/drain electrode 15 on thesubstrate 10. For example, a conductive layer may be deposited on asubstrate and then the conductive layer may be patterned to form thesource/drain electrode. The source/drain electrode may include a metal,for example, molybdenum. A buffer layer 16 may be formed on thesubstrate before forming the source/drain electrode is formed.

S43. As shown in FIG. 4B, forming the second semiconductor layer 14 onthe source/drain electrode 15. For example, an amorphous siliconmaterial can be deposited on the source/drain electrode and be doped,and then the amorphous silicon material is patterned to remove a portionlocated in the channel region, thereby forming a second semiconductorlayer. According to some embodiments of the present disclosure, thedoping may be in-situ doping performed during the deposition, or may bedoped separately after the deposition.

S45. As shown in FIG. 4C, forming the first semiconductor layer 11 onthe second semiconductor layer 14. For example, an amorphous siliconmaterial may be deposited on the second semiconductor layer 14 to form afirst semiconductor layer.

FIGS. 5A-5C are schematic views of a method for forming a firstsemiconductor layer, a second semiconductor layer, and a source/drainelectrode according to an embodiment of the present disclosure. In theembodiment shown in FIGS. 5A-5C, forming the first semiconductor layer,the second semiconductor layer, and the source/drain electrode includes:

S51. As shown in FIG. 5A, forming the first semiconductor layer 11 onthe substrate 10. For example, an amorphous silicon material may bedeposited on a substrate to form a first semiconductor layer. A bufferlayer may be formed on the substrate before the first semiconductorlayer 11 is formed.

S53. As shown in FIG. 5B, forming the second semiconductor layer 14 onthe first semiconductor layer 11. For example, an amorphous siliconmaterial may be deposited on the first semiconductor layer and be doped,and then the amorphous silicon material is patterned to remove a portionlocated in the channel region, thereby forming a second semiconductorlayer.

S55. As shown in FIG. 5C, forming the source/drain electrode 15 on thesecond semiconductor layer 14. For example, a conductive layer may bedeposited on the second semiconductor layer, and then the conductivelayer may be patterned to form the source/drain electrode.

According to some embodiments of the present disclosure, a method suchas chemical vapor deposition (CVD) may be adopted to form asemiconductor layer.

The specific embodiments have been described, and are not intended tolimit the scope of the disclosure. In fact, the novel embodimentsdescribed herein can be implemented in a variety of other forms. Inaddition, various omissions, substitutions, and changes in the form ofthe embodiments described herein may be made without departing from thespirit of the disclosure. The following claims and their equivalents areintended to cover such forms or modifications that fall within the scopeand spirit of the disclosure.

1. A thin film transistor comprising: a substrate; a first semiconductorlayer, a gate dielectric layer, and a gate electrode sequentiallystacked on the substrate, wherein the first semiconductor layer has afirst portion located in a channel region of the thin film transistorand a second portion located in source/drain regions of the thin filmtransistor and on both sides of the first portion, wherein the secondportion and first sub-portion adjacent to the second portion of thefirst portion comprise an amorphous semiconductor material, and whereina second sub-portion, between the first sub-portions, of the firstportion comprises a polycrystalline semiconductor material; and a secondsemiconductor layer located in the source/drain regions and in contactwith the second portion, wherein a conductivity of the secondsemiconductor layer is higher than a conductivity of the amorphoussemiconductor material.
 2. The thin film transistor according to claim1, wherein the second semiconductor layer is in contact with a surfaceof the second portion facing the substrate.
 3. The thin film transistoraccording to claim 1, wherein the second semiconductor layer is incontact with a surface of the second portion away from the substrate. 4.The thin film transistor according to claim 2, wherein a doping type ofthe first semiconductor layer and a doping type of the secondsemiconductor layer are an N-type, and wherein an N-type carrierconcentration of the second semiconductor layer is greater than anN-type carrier concentration of the first semiconductor layer.
 5. Thethin film transistor according to claim 2, wherein a doping type of thefirst semiconductor layer and a doping type of the second semiconductorlayer are a P-type, and wherein a P-type carrier concentration of thesecond semiconductor layer is greater than a P-type carrierconcentration of the first semiconductor layer.
 6. The thin filmtransistor according to claim 2, wherein a doping concentration of thefirst semiconductor layer is between 10¹⁷ ions/cm³ and 10¹⁹ ions/cm³,and wherein a doping concentration of the second semiconductor layer isbetween 10¹⁹ ions/cm³ and 10²¹ ions/cm³.
 7. The thin film transistoraccording to claim 1, wherein the polycrystalline semiconductor materialcomprises polysilicon, and wherein the amorphous semiconductor materialcomprises amorphous silicon.
 8. The thin film transistor according toclaim 1, further comprising a source/drain electrode on a side of thesecond semiconductor layer facing away from the second portion.
 9. Amethod for manufacturing a thin film transistor, the method comprising:forming a first semiconductor layer, a gate dielectric layer, and a gateelectrode sequentially on a substrate, wherein the first semiconductorlayer has a first portion located in a channel region of the thin filmtransistor and a second portion located in a source/drain region of thethin film transistor and on both sides of the first portion, wherein thesecond portion and first sub-portions, adjacent to the second portion,of the first portion comprise an amorphous semiconductor material, andwherein a second sub-portion, between the first sub-portions, of thefirst portion comprises a polycrystalline semiconductor material; andforming a second semiconductor layer in the source/drain regions and incontact with the second portion, wherein a conductivity of the secondsemiconductor layer is higher than a conductivity of the amorphoussemiconductor material.
 10. The method for manufacturing a thin filmtransistor according to claim 9, wherein forming the first semiconductorlayer comprises: forming a first semiconductor material layer comprisingthe amorphous semiconductor material, the first semiconductor materiallayer comprising a middle portion as the first portion and edge portionsas the second portion, the edge portions being on both sides of themiddle portion; and converting a portion, corresponding to the firstsub-portion, of the middle portion of the first semiconductor materiallayer into the polycrystalline semiconductor material.
 11. The methodfor manufacturing a thin film transistor according to claim 10, whereinthe converting comprises laser annealing the amorphous semiconductormaterial.
 12. The method for manufacturing a thin film transistoraccording to claim 11, wherein the laser annealing comprises using amicro lens array mask.
 13. The method for manufacturing a thin filmtransistor according to claim 9, further comprising forming asource/drain electrode on a side of the second semiconductor layerfacing away from the second portions.
 14. The method for manufacturing athin film transistor according to claim 13, wherein forming the firstsemiconductor layer, the second semiconductor layer, and thesource/drain electrode comprises: forming a source/drain electrode onthe substrate; forming the second semiconductor layer on thesource/drain electrode; and forming the first semiconductor layer on thesecond semiconductor layer.
 15. The method for manufacturing a thin filmtransistor according to claim 13, wherein forming the firstsemiconductor layer, the second semiconductor layer, and thesource/drain electrode comprises: forming the first semiconductor layeron the substrate; forming the second semiconductor layer on the firstsemiconductor layer; and forming the source/drain electrode on thesecond semiconductor layer.
 16. The method for manufacturing a thin filmtransistor according to claim 14, wherein forming the firstsemiconductor layer and the second semiconductor layer comprises usingCVD.
 17. The method for manufacturing a thin film transistor accordingto claim 9, wherein the polycrystalline semiconductor material comprisespolysilicon, and wherein the amorphous semiconductor material comprisesamorphous silicon.
 18. The thin film transistor according to claim 3,wherein a doping type of the first semiconductor layer and a doping typeof the second semiconductor layer are an N-type, and wherein an N-typecarrier concentration of the second semiconductor layer is greater thanan N-type carrier concentration of the first semiconductor layer. 19.The thin film transistor according to claim 3, wherein a doping type ofthe first semiconductor layer and a doping type of the secondsemiconductor layer are a P-type, and wherein a P-type carrierconcentration of the second semiconductor layer is greater than a P-typecarrier concentration of the first semiconductor layer.
 20. The thinfilm transistor according to claim 3, wherein a doping concentration ofthe first semiconductor layer is between 10¹⁷ ions/cm³ and 10¹⁹ions/cm³, and wherein a doping concentration of the second semiconductorlayer is between 10¹⁹ ions/cm³ and 10²¹ ions/cm³.